Taiwan

Imec’s 2041 Angstrom Roadmap: High-NA EUV Becomes the Standard for Advanced Foundries

Imec, a leading semiconductor R&D center, announced its updated technology roadmap extending to the A2 node by 2041, emphasizing High-NA EUV as critical for future 2D scaling.

AsiaAI Publisher · August 31, 2026 · 2 min read · Source: 科技新報 TechNews

Semiconductors & Hardware

What this means

Why it matters: Imec’s roadmap to 2041 confirms that 2D scaling, driven by extreme lithography, remains the primary engine for reducing cost-per-transistor, despite the industry’s focus on 3D packaging and heterogeneous integration. This perspective contrasts with some Western narratives that overemphasize packaging as a standalone scaling solution, underscoring that the physical foundation of future chip performance still relies on relentless dimensional shrinkage at the most fundamental level. For foundries like TSMC, this means sustained, massive capital expenditure on cutting-edge EUV tools and the global ecosystem supporting them.

For Western readers: Western integrated device manufacturers (IDMs) and fabless companies must internalize that the fundamental cost-per-transistor gains will continue to be driven by 2D scaling and advanced lithography like High-NA EUV, rather than solely relying on packaging innovations. Plan R&D and capital allocation with the understanding that access to these lithography advancements will remain a critical bottleneck and differentiator for years to come, with ASML and the imec ecosystem holding the keys.

What to watch: Monitor ASML’s delivery and ramp-up of High-NA EUV systems, particularly the EXE:5200 series, as its performance metrics and integration into foundry processes will dictate the real-world pace of this roadmap.

Imec, a leading semiconductor R&D center, announced its updated technology roadmap extending to the A2 node by 2041, emphasizing High-NA EUV as critical for future 2D scaling. The organization’s advanced patterning team has been renamed ‘Angstrom Patterning‘ to reflect the industry’s entry into an ‘atomic precision era’ where defect tolerance and measurement accuracy approach zero. High-NA EUV is deemed essential to achieve sub-nanometer overlay accuracy and overcome the physical limits of current lithography at increasingly smaller pitches, allowing for greater design freedom.

This announcement from imec, a consortium backed by major chipmakers, signals the long-term technological trajectory for advanced semiconductor manufacturing, directly impacting TSMC, Samsung, and Intel. It solidifies High-NA EUV’s role as the foundation for future chip generations, extending well beyond the current decade, and underscores the increasing R&D investment required to push transistor scaling into the Angstrom era.

For the wider picture, see Taiwan Semiconductor Ecosystem.

Original source (Taiwanese Chinese)

埃米時代圖形化革命，imec 揭示 High-NA EUV 邁向 2041 年技術藍圖

科技新報 TechNews

This story appeared in AsiaAI.FYI Issue #82.